Integrated circuits continue to advance such that an increasing number of devices, and hence more circuit functions, are integrateable onto a single semiconductor device. Not only are the number of integrateable circuit functions increasing, but the complexity of the circuits are increasing as well. In addition to continual increases in density and complexity, engineers concurrently find ways to decrease design cycle times of these integrated circuits. One well known integrated circuit type that uses a design methodology that improves cycle times is the application specific integrated circuit (ASIC).
A substantial benefit of designing with ASICs is the ability, using sophisticated computer aided design (CAD) techniques, to quickly define a design using predefined or compiled library elements and realize that design in silicon. ASICs rely upon the use of predefined macros, for example, adders, multipliers, microprocessor cores, control functions, memories, etc. These macros can be predefined to the level of having all mask layers defined or may merely reside in software. Macros that reside in software are referred to as soft macros or paramaterized macros.
Soft or paramaterized macros describe a circuit or logic function that may be modified according to certain input parameters before being defined in the several mask layers. ROM circuits play an important role in systems and due to the needed flexibility of storing different amounts of memory in varying word lengths ROMs are often available as a soft or paramaterized macro. For example, a soft ROM macro (growable ROM) may be used in one system that requires 2K bits of memory organized in eight bit word lengths. The same growable ROM could very quickly be re-compiled to provide 4K words organized to provide sixteen bit word lengths.
High density ROMs typically rely upon a sensing scheme that operates upon a single bitline for each column of memory cells. Higher performance, however, generally dictates a sense amplifier design having dual inputs operating in a differential mode wherein the second input is a reference signal. During a read cycle the reference bitline must track an average transient response of a data bitline representing a logic one and the transient response of a data bitline representing a logic zero. Maintaining accurate reference bitline tracking in a growable ROM is complicated by the fact that the electrical characteristics of the data bitlines change not only in response to specific programming but also according to their location in the memory array. The change in such electrical characteristics is especially exacerbated in larger arrays.
The two data values in the memory array are programmed by either the presence or absence of a bitline contact to a drain of each memory cell transistor, wherein that transistor is an n-channel field effect transistor (NFET). When a contact is present, the corresponding selected bitline discharges during the read cycle. When a contact is not present, the corresponding selected bitline does not discharge but remains precharged. A design goal is to allow the reference bitline to discharge at half the rate the data bitline discharges (contact present). This has been accomplished heretofor by connecting two adjacent bitlines together and programming one of the two cells that share a same wordline. The dual cells present a doubled capacitive load causing the discharge rate of the reference bitline network halve.
When a contact is absent in a data bitline cell or the reference bitline cell the junction capacitances associated with the drain contact is not added to the corresponding data or reference bitline. Worst case capacitive loading occurs in a data bitline having a contact in each memory cell of that column. An accurate reference bitline to reflect this scenario would also have contacts in every cell. The inventors of the present invention described herein recognize that such a similarly programmed reference bitline would discharge double the current that is associated with the double capacitance and the target reference bitline discharge rate of half that of the data bitline discharge rate will not be achieved.
Accordingly it is desired to provide a ROM having localized reference bit lines that track a target discharge rate of one half the discharge rate of a data bitline regardless of the contact programming of the memory cells of the columns of memory cells.